1. Field of the Invention
The present invention relates to digital memory circuitry, and more specifically, to sense amplifier circuitry for embedded dynamic random access memory (eDRAM) circuits.
2. Description of Related Art
Nearly all personal computers use some form dynamic random access memories (DRAM). Each DRAM cell can store one bit of information. Reading, or detecting, the bit stored in a DRAM cell destroys the charge in the cell defining the bit, which must then be replenished in order to maintain the stored bit. DRAM sense circuits are used to read the bit stored in cells, and then replenish the charge in the cell to maintain the bit, either as a logical “1” or “0”. DRAM circuitry has been adapted for a number of uses, including for example, embedded dynamic random access memory (eDRAM) circuits.
An eDRAM is a DRAM that is integrated on the same die or configured within the same package as its processor or ASIC (Application Specific Integrated Circuit), or like types of logic or circuitry. Since eDRAM circuitry embeds DRAM cells with their corresponding processor or ASIC, eDRAM avoids the need for I/O signals to travel between separate memory chips. As such, eDRAM tends to be faster and more efficient, using less power and increasing the performance of the processor and memory functions than previous DRAM technology. Nonetheless, conventional eDRAM circuits do suffer from certain drawbacks, leaving room for improvement. For instance, conventional eDRAM sense amplifiers can connect to only a limited number of cells, typically no more than thirty-two cells. For additional cells designers must gang together additional conventional sense circuitry. One reason for this is that conventional eDRAM sense circuits lack enough sensitivity in their amplifier section. If too many cells are connected to a conventional eDRAM sense circuit then the amplifier section cannot accurately detect individual released charges resulting in data errors. Another drawback related to the lack of amplifier sensitivity is that the access speeds of conventional eDRAM sense circuits tend to be limited, thus inhibiting further increases in processor clock speed.
The present inventors recognized the need for improved eDRAM sense amplifier circuitry.